Author: Hayden Richards
Date/Time: May 12th, 2025 at 9:30 AM EST
Location: Martin Hall, EGR-2164
Committee members:
- Professor Abhijit Dasgupta, Chair
- Professor Peter Sandborn
- Professor Michael Osterman
- Professor F. Patrick McCluskey
- Professor Norman Wereley (Dean’s Representative)
Title: EFFECTS OF MECHANICAL SHOCK ON RELIABILITY OF EMBEDDED COMPONENT
INTERCONNECTS IN PRINTED HYBRID ELECTRONICS AT ELEVATED TEMPERATURES
Abstract:
The advantages of Printed Hybrid Electronic (PHE) assemblies are of
considerable interest to designers of electro-mechanical systems,
especially for applications in extreme environments. With additional
development, PHEs may offer reliability advantages over traditional
electronic packages in fields like aerospace or applications such as
conformal circuits or integrated sensors. For this work, passive
components were recessed into machined cavities in injection-molded
polysulfone domes and beams by way of a unique ‘mill-and-fill’ method
combining traditional subtractive milling with extrusion-based paste
printing. The components were interconnected to printed silver traces
using printed solder, with circuits then formed from the silver
traces. These assemblies were subject to large strains caused by
mechanical shock at acceleration levels up to 100,000 g and at
temperatures from 25 °C to 125 °C
The populated beam specimens were subjected to drop
testing in a clamped-clamped configuration without secondary impact
using an accelerated-fall drop tower with dual mass shock amplifier,
resulting in substrate strain magnitudes of up to 50,000 µm/m at rates
up to ~1000 /s. Trace degradation characteristics were first
assessed, then the number of drops to failure (as defined by component
separation from the substrate) were documented across four different
component locations on a beam specimen, providing failure data for
four different strain histories. These four strain histories were
compiled across a total of seven different test points ranging from
25,000 g to 100,000 g and 25 °C to 125 °C. Concurrently, a combined
global-local finite element model was used to simulate the physical
response of the sintered silver within the trace adjacent to the
recessed component. This model was matched to experiments by direct
strain measurement in the substrate, supported by digital image
correlation.
Circuit failure occurred due to component separation from
the substrate caused by cracking within the sintered silver beneath
the soldered interconnect – a failure mode common across all
acceleration levels and temperatures. The dependence of rates of
degradation and failure on acceleration level was quantified based on
strain levels expected within the silver trace. Plastic strain
magnitude was used as the basis for damage accumulation in the
sintered silver. Collectively the experimental results and simulation
data were integrated by means of a cumulative damage model to generate
an application-agnostic low-cycle fatigue curve for the sintered
silver from 25-125 °C.